SAN JOSE, Calif. — Simple assertions should be part of future Verilog IEEE standards, according to panelists at the DVCon Design and Verification Conference here Monday (Feb. 24). But several said ...

In an EDA Views column posted to EEdesign April 4, 2003, Mitch Weaver of Cadence Design Systems wrote of the need to extend the Verilog standard to support ever-increasing design sizes. Mr. Weaver ...