Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Design-Reuse

PLDA and Aldec Announce PCI Express DMA IP Supporting Advanced Verification Tools for FPGA Development

PLDA’s EZDMA IP and Aldec’s Riviera-PRO and Active-HDL tools enable ease-of-design and robust verification into design environments SAN JOSE, Calif. & HENDERSON, Nev.-- April 28, 2011--PLDA, the ...
EDN

Aldec releases Active-HDL 7.1

Well known for its mixed-language simulation and advanced design tools for ASIC and FPGA devices, Aldec, Inc., has announced the release of Active-HDL 7.1. Active-HDL 7.1 is an FPGA and ASIC design ...
Design-Reuse

Aldec delivers Global Project Management for Complex FPGA Designs with the latest release of Active-HDL

Henderson, NV – October 23, 2013 – Aldec, Inc., today announced the immediate availability of Active-HDL™ version 9.3, introducing a revolutionary approach to the increasing challenges of global ...
New Electronics

Aldec platform supports newest fpga devices

Electronic design verification specialist, Aldec has launched an HDL based fpga design and simulation platform that supports the newest fpga devices. According to Aldec, Active-HDL version 9.1 is a ...
Business Wire

Aldec Releases Active-HDL 10.1 with 64-bit Simulation Support

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...
Business Insider

QuickLogic Announces Partnership with Aldec for eFPGA Simulation Flow

SUNNYVALE, Calif., Feb. 20, 2018 /PRNewswire/ -- QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, display bridge and programmable ...
New Electronics

Aldec enhances Active-HDL to support new features

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has announced that it has enhanced Active-HDL to support new features within ...
EE Herald

Avnet to distribute Aldec's Active-HDL in Asia

Aldec, Inc., has announced that it has entered into a distribution agreement with Avnet Electronics Marketing Asia. Under the terms of the agreement, Avnet Electronics Marketing will promote and ...
EDN

Active-HDLTM provides advanced verification environment for all QuickLogic FPGA and ESP families

QuickLogic Corporation and Aldec, Inc.,announced that QuickLogic is integrating Aldec's Active-HDLTM Lite verification environment into its QuickWorks QuickLogic and Aldec have partnered to provide ...